1. Field of the Invention
The present invention relates to technique of an error correction processing, and more particularly to a method and system for performing error detecting and correcting process with a memory having a small memory capacity for a system for multiplexing FM sound broadcasting with a subcarrier data channel, for example, a mobile receiving type FM multiplex broadcasting of a DARC (Data Radio Channel) system.
2. Description of the Related Art
In an FM multiplex broadcasting system, there are known three systems: a DARC (Data Radio Channel) system which is the standard system in Japan, a portable receiving system and a RDS (Radio Data System) which is developed in Europe and is adopted as the international standard system. Error correction codes are different from each other between the three systems. As the error correction code, the DARC system uses a product code of a (272, 190) code, the portable receiving system uses the (272, 190) code, and the RDS uses a (26, 16) code.
In the product code, error correction codes are added to data bits in both of a column direction and a row direction to allow error correction in both of the column direction and the row direction. In the DARC system, 272 data blocks are set as the one frame data, and each data block is composed of a data section of 190 bits including CRC and a parity section of 82 bits. One data block is transmitted during about 18 ms. In accordance with, the time which is required to transmit one frame data is about 5 seconds. This one frame data forms the product code of the (272, 190) code.
Next, the structure of the frame format B used in the DARC system as a frist conventional example is shown in FIGS. 3A and 3B. In this frame format, the frame data is transmitted in the data form in which a parity block is interleaved between the data blocks. In accordance with, when the error correction of the column direction is performed actually, it is necessary for the transmission frame data to be set in the state in which this interleaving state is eliminated. In other words, the transmission frame data is necessary to be converted into a data format of a data section of 190 blocks from the head of the frame data and a parity data section of 82 blocks subsequent to the data section.
The conventional error correcting operation using the product code of the (272, 190) code will be described below.
A conventional error correction processing system is composed of a data inputting section, an error detecting and correcting section and a frame memory unit. The data inputting section receives and outputs the data blocks each having 272 bits including an error correction code data.
The error detecting and correcting section inputs the data blocks to perform an error detecting and correcting process, and outputs the data block to which the error correction has been performed if the error correction is possible. Also, the error detecting and correcting section outputs an error signal and the data block to which the error correction has been performed if the error correction is impossible. The frame memory unit inputs and stores the data block which is outputted from the error detecting and correcting section.
The error detecting and correcting process will be described with reference to FIGS. 1A to 1C. First, the data block of 272 bits is inputted to the data input section and then is transferred to the error detecting and correcting section in step S102. In the error detecting and correcting section, an error detecting and correcting process (to be simply referred to as an "error correcting process" hereinafter) is performed to the transferred data block in a step S104. If any error is not detected in a step S106, the data block is determined to be a correct data and the data block is outputted to and stored in the frame memory unit in a step S114. Also, when any error is detected in the step S106, the error correcting process is performed in the error correcting section in a step S108. As a result, a data block after the error correcting process is outputted to and stored in the frame memory unit in the step S144. At this time, the error signal is set to be "affirmative", if there is any error in the data block after the error correcting process, and also is set to be "negative" if there is not any error.
The above-mentioned error correcting process is performed 272 times, and the frame data after the error correcting process for one frame, i.e., the 272 data blocks is stored in the frame memory which is shown in FIGS. 3A and 3B. FIG. 2A shows an example of the frame data after the error correcting process, and a ".circle-solid." symbol shows an error bit position in FIG. 2A. The first error correcting process in the row direction for one frame is ended with the above process.
Next, the error correcting process in the column direction of the frame memory is performed. FIG. 1B shows a flow chart illustrating the error correcting process in the column direction.
The data block of 272 bits in the column direction is transferred to the error detecting and correcting section. Then, the error correcting process in the column direction is performed as in the error correcting process in the row direction, as shown in FIG. 1A.
The error correcting process in the column direction is performed 272 times. Then, the data after the first error correcting process in the row detection and the error correcting process in the column direction are performed to the frame data for one frame, i.e., 272 data blocks is stored in the frame memory.
FIG. 2B shows the result of the first error correcting process in the row detection and the error correcting process. A ".largecircle." symbol of FIG. 2B shows the bit which is corrected by the error correcting process in the column direction. Also, the ".circle-solid." symbol shows the error bit after the first error correcting process in the row direction and the error correcting process in the column direction are performed.
Further, the second error correcting process in the row direction is performed to the frame data stored in the frame memory after the error correcting process in the column direction. The operation will be described with reference to a flow chart of FIG. 1C. The data block of 272 bits in the row direction is transferred from the frame memory unit to the error detecting and correcting section. Then, the second error correcting process is performed in the row direction, as in the first error correcting process in the row direction shown in FIG. 1A.
The second error correcting process in the row direction is performed 272 times. Then, data after the first error correcting process in the row direction, the error correcting process in the column direction and the second error correcting process in the row direction have been performed is stored in the frame memory, as shown in FIG. 2C. FIG. 2C shows an example of the frame data after the first and second error correcting processes in the row direction and the error correcting process in the column direction. The ".circle-solid." symbol shows the error bit after the first error detecting and correcting process in the row direction, the error correcting process in the column direction and the second error correcting process in the row direction. Also, the ".largecircle.", symbol shows the bit which is corrected by the second error correcting process in the row direction.
The above-mentioned processing is the contents of the error correcting process to the one frame data in the conventional error correcting system.
In this case, the frame memory is divided into two section, i.e., a frame memory A and a frame memory B, as shown in FIGS. 3A and 3B. The frame memory has a memory capacity for two frame data, i.e. about 18 Kbytes. A data section of 190 data blocks from the head of the frame data and a parity section of 82 blocks subsequent to the data section are arranged in each of the frame memories A and B.
After the 272 data blocks for one frame are stored in the frame memory A, the 272 data blocks for the next frame starts to be stored in the frame memory B. At this time, before the entire frame data of the 272 data blocks for the next frame are completely stored in the frame memory B, the error correcting process in the row direction and the second error correcting process in the column direction to the frame data of 272 data blocks which has been stored in the frame memory A must be completed. In accordance with, until the frame data for the next frame is stored, the first error correcting process in the row direction is performed 272 times, the error correcting process in the column direction is performed 272 times, and the second error correcting process in the row direction is performed 190 times. That is, it is totally 734 times. These processes are alternately performed to the frame memory A and the frame memory B.
As mentioned above, in the conventional error correcting system, the first error correcting process in the row direction is performed every time one data block is received. The interleaving state of the parity block is canceled after the first error correcting process and is stored in the frame memory. When data for one frame after the first error correcting process in the row direction is stored in the frame memory, the error correcting process in the column direction is performed to the frame data of 272 data blocks. Further, the second error correcting process in the row direction is performed to the frame data of 190 data blocks. In this case, because the remaining 82 data blocks are a parity section, the second error correcting process in the row direction is not needed.
In this case, during the execution of the error correcting process in the column direction to the frame data stored in the frame memory A, the first error correcting process in the row direction is performed to each data block of the frame data for the next frame. Also, the canceling process of the interleaving, and then the storing process in the frame memory B are performed to each data block of the frame data for the next frame. However, to simplify the control of access to the frame memory, another frame memory for one frame is needed in the conventional error correcting system.
The frame memory capacity for one frame is about 9 Kbytes. Since the frame memories for two frames becomes necessary, the frame memory capacity becomes about 18 Kbytes in the conventional error correcting system.
Also, since the error correcting process is performed by peripheral hardware built in a microcomputer, there is a problem in that the influence to a chip size can not be avoided because of the memory capacity of 18 Kbytes, if a frame memory is further built in the microcomputer.
In addition, an error correcting decoding circuit is described in Japanese Examined Patent Application (JP-B-Heisei 1-55788). In this reference, the error correcting decoding circuit is composed of designating and inputting means, a data register, a majority determining circuit, loading means and an output data selecting circuit. The designating and inputting means designates to reduces a (l, k) code to (k-n) bits, wherein the (l, k) code having k data bits and (l-k) parity bits and n is the number of bits of "0",. The m-bit data register has a plurality of output bits and m is equal to or smaller than k. The loading means loads the (k-n) data bits before correction to the m-bit data register based on the designation of the designating and inputting means. The output data selecting circuit selects and outputs one from among the output bits of the m-bit data register based on a signal from the designating and inputting means. Thus, an error of code data is corrected based on a majority determining error correcting system using a difference set cyclic code.
An error correcting decoding system is described in Japanese Examined Patent Application (JP-B-Heisei 2-11184). In this reference, the error correcting decoding system includes a majority determining circuit using a majority determining difference set cyclic code, a syndrome register and a data register. A subtracting circuit is added to the majority determining circuit. A determination threshold value of the majority determining circuit is set to a specific value which is within the number of input elements of the majority determining circuit. A specific number is sequentially subtracted from the determination threshold value via the subtracting circuit until the determination threshold value reaches the specific value, to correct and decode data.
An error correcting decoding system is described in Japanese Examined Patent Application (JP-B-Heisei 3-76612). In this reference, a packet of 272 bits is formed from a majority determining difference set cyclic code using 273 data bits, 191 information bits and 82 parity bits. A data signal is formed of 272 data bits, 190 information bits and 82 parity bits. Correction is performed based on the output state of the syndrome register for the data signal. A head bit is shifted to perform the correction again only when the syndrome register is all set to 0 after the correction. Thus, the probability that more than 9 error bits are corrected for one packet is increased.